Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach

Design and verification of clockless Advanced Encryption Standard (AES) crypto-hardware for improved side-channel attack resistance

The Advanced Encryption Standard (AES) is the most widely used symmetric key algorithm standard in different security protocols. The AES was very reliable in providing security for data until a few years ago, when researchers proved the Side Channel Attacks (SCA) like power analysis were successful in compromising this security. This thesis focuses on designing effective countermeasures against the SCA\u27s, by exploring the usage of an Asynchronous logic based design approach, called Null Convention Logic (NCL). This work discusses the design of NCL based subset of AES cryptosystem. The performance benefits of this novel cryptosystem are presented by making qualitative comparisons to the traditional synchronous design approach. This thesis is composed of two papers. In paper I, the design and evaluation of SCA resistant NCL based AES Round Function is presented. This design approach leverages on the special properties of NCL to achieve a uniform and lower signal to noise ratio and thereby improves SCA resistance. Performance evaluation of the proposed design by using Weighed Average Simultaneous Switching Outputs (WASSO) analysis is presented. Paper II, discusses the design and evaluation of NCL based AES Key Expander, hardware implementation of the entire NCL based subset of AES cryptosystem on FPGA board. Performance evaluation of the proposed approach, by analyzing power traces obtained from hardware implementation of proposed design and the traditional synchronous design is presented. Using both the software simulations and hardware simulations the benefits of this proposed approach are discussed --Abstract, page iv

Design and Evaluation of Side Channel Attack Resistant Asynchronous AES Round Function

A novel Asynchronous AES Round Function design is proposed in this paper, which offers increased Side-Channel Attack (SCA) resistance by combining the advantages of dual rail encoding and clock free operation. The design is based on a Delay Insensitive (DI) logic paradigm known as Null Convention Logic. By reducing switching activity and thereby Signal-to-Noise (SNR) ratio, the proposed design leaks far less side channel information than traditional approaches and this feature boosts SCA resistance of this approach. Functional verification and WASSO analysis simulations were carried out on both synchronous approach and the proposed NCL based approach using Xilinx simulation tools to validate the claims related to benefits of employing this novel dual rail design approach